1. Field of the Invention
This invention relates generally to wafer cleaning in a semiconductor manufacturing process, and more particularly to site-specific wafer backside particle and contamination removal prior to a lithographic process.
2. Description of the Related Art
During semiconductor fabrication, wafers are processed via a plurality of processing modules that create the various dielectric and metal layers that comprise the semiconductor devices. To ensure proper processing, the wafers generally are cleaned at various points during the manufacturing process to remove particles that may affect the device fabrication. One such cleaning operation typically is performed prior to the lithography process.
Lithography is a well known field and includes both electron beam and photolithography. A typical application of lithography is for defining patterns onto photo or electron sensitive resist that is coated on a substrate, which typically is a semiconductor wafer or a reticle blank for semiconductor fabrication. The lithography process defines a pattern on the resist that is then developed and used for subsequent etching or other steps.
FIG. 1A is a diagram showing a prior art lithography system 100. The lithography system 100 includes a lithography tool 102, which exposes photo resist on the surface of a wafer 104. Generally, the wafer 104 is held in place during the lithography processing using a chuck 106 having, in this example, a plurality of pins 108 that support the wafer 104.
In operation, the lithography tool 102 includes a reticle (mask) in which a beam of light is directed through a mask to image a pattern onto the photo resist of the wafer 104. In addition, a beam can be directed in a raster or vector scan onto the resist of the wafer 104. The scanned beam is turned on and off in order to expose or not expose various portions of the resist. In lithography an important goal is uniformity of each instance of an identical feature defined by the lithography process. The features are the elements imaged onto the substrate. There can be systematic variations in feature sizes that are determined by the feature's location on the substrate and which arise from a variety of causes.
Unfortunately, problem ‘hot spots’ can occur during critical lithographic process steps, which can cause the entire wafer 104 to require reworking. Hot spots occur when particles 110 on the backside of the wafer 104 effectively shift the wafer 104 up locally, causing local depth of focus problems, as described in greater detail subsequently with reference to FIG. 1B. In particular, particles having a size greater than about 150 nm can cause local shifts of sufficient size to create local depth of focus problems. The severity of local shift problems often depends on the wafer location where the local shift occurs.
FIG. 1B is a diagram showing an exemplary depth of focus range 150 for a conventional lithography process. The depth of focus range 150 is the range within which the lithography tool 102 can properly expose the resist on the surface of the wafer 104. As shown in FIG. 1B, the surface of the wafer 104 varies, depending on the structures being fabricated on the wafer 104. As a result, the severity of local shift problems often depends on the wafer location where the local shift occurs. For example, when a particle is located on the backside of the wafer 104 below point 152, point 152 could be shifted up to point 152′. Since point 152′ is still located within the depth of focus range 150, the affect from the hot spot generally will be relatively small.
However, when a particle is located on the backside of the wafer 104 below point 154, which is located on a higher point of the wafer 104 than point 152, point 154 could be shifted up to point 154′. Since point 154′ is located outside the depth of focus range 150, the affect from the hot spot can cause exposure errors which will require the wafer 104 to be reworked. In particular, when the resist is shifted outside the depth of focus range 150 underexposure and overexposure of the resist can occur, as described below with reference to FIGS. 2A and 2B.
FIG. 2A is a diagram showing an underexposed resist layer 200. After development, the resist mask in the example of FIG. 2A should have a pattern as defined by resist pattern 202. However, because of a shift outside the depth of focus for the lithography tool, the resist mask includes an underexposed resist portion 204. As will be apparent to those skilled in the art, the underexposed resist portion 204 can prevent areas below the underexposed resist portion 204 in the underlying layer 206 from being etched, and a change in critical dimension of the feature being defined by the lithography process. As a result, the etch pattern will be incorrect, causing the device to function improperly. An incorrect etch pattern can also result from overexposure of the resist, as described next with reference to FIG. 2B.
FIG. 2B is a diagram showing an over exposed resist layer 250. As with FIG. 2A, after development the resist mask in the example of FIG. 2B should have a pattern as defined by resist pattern 202. However, because of a shift outside the depth of focus for the lithography tool, the resist mask can include bowed resist portions. For example, overexposure can bow the resist pattern 202, causing the resist pattern to comprise both sections 202 and bowed sections 252. As will be apparent to those skilled in the art, the overexpose resist comprising sections 202 and sections 252 can adversely affect areas below the overexposed bowed resist portion 252 in the underlying layer 206 from during etch. As a result, the etch pattern will be incorrect, causing the device to function improperly.
Etch errors typically are discovered during critical dimension checks where the critical dimensions of the wafer features are checked. When the errors are discovered the wafer must be reworked. Reworking requires the wafer to be removed, cleaned, recoated, baked, and re-patterned using the lithography tool. It is not unusual for conventional lithography systems to require from about 10%–20% rework without effective wafer backside cleaning prior to lithography processing, and maintenance of the cleanliness between the cleaning step and the lithography step.
In view of the foregoing, there is a need for backside cleaning methods that remove backside particles and contamination prior to a lithographic process. The methods should provide efficient and effective backside cleaning without requiring undue cost and time to perform.